(1) The trimmed FF/Latch warning is not due to non-blocking assignments. It is from 24 bits of the temp_buff
register always being assigned to zeros. The RHS is 16bits; i_msb
(4 bits), q_msb
(4 bits), and temp_buff[31:24]
(8 bits). And you are assigning it to a 32bit value. The assignment:
temp_buff <= {i_msb,q_msb,temp_buff[31:24]};
Is equivalent to:
temp_buff <= {16'h0000, i_msb,q_msb,temp_buff[31:24]};
This means temp_buff[31:16]
will always be zero can can be optimized out. temp_buff[7:0]
can also be optimized out to constant zeros because it is assigned to temp_buff[31:24]
which is a constant 0. Perhaps you meant you shift right 8 bits like so:
temp_buff <= {i_msb,q_msb,temp_buff[31: 8 ]};
(2) You are correct that wires should not be assigned with any always block (or initial block). However you could have turned the wire
to a reg
. It is a miss conception that reg
is for registers only (FF/Latches). reg
in a properly coded combinational block will create combinational logic (no FF or Latches). Property meaning the reg
is assigned within every branching condition withing the always block, else it infers a latch. Example
module my_rx_dsp0_custom
/* ... your original code ... */
output reg [31:0] bb_sample,
output reg bb_strobe //high on valid sample
);
/* ... your original code ... */
always @(posedge clock)
if(ddc_out_strobe) begin
temp_buff <= {i_msb,q_msb,temp_buff[31:8]};
count <= (count==2'd3) ? 2'd0 : (count+1);
end
always @*
begin
i_msb = ddc_out_sample[31:28];
q_msb = ddc_out_sample[15:12];
bb_strobe = (count==2'd3);
bb_sample = bb_strobe ? temp_buff : 32'd0;
end
assign ddc_out_enable = enable;
/* ... your original code ... */