(VHDL) How to assign a summation result partially in one clock

Question

I am trying to implement this on VHDL:

a<=(b+c)/16;

I have tried this, but synthesis did not accept it.

signal b,c   : std_logic_vector(7 downto 0);
signal a     : std_logic_vector(8 downto 0);
signal dummy : std_logic_vector(3 downto 0);

(a & dummy) <= ("00000" & b) + ("00000" & 'c');

then I was to use a but it failed. (Operation & cannot be associated with a formal of mode OUT.)

Any suggestions? Thanks, Cem

Answer 1

Use ieee.numeric_std and declare a,b,c,dummy as unsigned rather than std_logic_vector. Or signed if that's what your application calls for.

Answer 2

Just use your first attempt and make that a, b and c are numerical types. std_logic_vector has no numerical meaning, so you can't do arithmetic on them.

Either make them all integers, or do as Brian suggests, and use ieee.numeric_std and the signed or unsigned vector types.