What's the motivation for a fpu to implement their registers in stack-based fashion?

Question

What's the motivation for a fpu to implement their registers in stack-based fashion? To my understanding other instructions-sets such as x86/sse use named registers. I can imagine the stack-based properties correspond with our thought of functions in general thus resulting in a more intuitive design for assembly programmers.

However I was curious whether or not there are some more tangible motivations i.e. technological advantages.

Answer 1

These architectures are not commonly seen in the field today, anymore. Back in the days though, both silicon space for registers and program code space were rare resources (as it is still the case in embedded environments nowadays). That pretty much sums up the two motivations behind such an architecture:

• ISA is much slimmer
  • less space for register coding is needed
  • less instructions for things like stack handling (obviously)
• simpler hardware designs
  • less register decode logic
  • very deterministic and mathematically well-understood behavior (the reason why virtual architectures like the Java Virtual Machine still use it)

Answer 2

This question can only be truely answered by the designer of the original 8087 himself, W. Kahan, who wrote about it on a short paper called "On the Advantages of the 8087's Stack".

From there:

• The 8087 stack is not really a "classical stack", you can access any register, not only the top two/three registers.
• Flat register set with two operands/instruction was impractical: there was a lack of encoding space for the coprocessor instructions which made one-operand instructions to be preferred (and a stack excels at that), and the number of registers it could have had (apparently 8 was impossible, it seems there was only enough space for 4 registers) was deemed insufficient for efficient computation of some common floating point operations.
• Stack overflow/underflow was supposed to happen infrequently, and be handled in software, giving the illusion of a much larger stack.

Answer 3

This is mainly only true for x86 because neither ARM nor PowerPC nor MIPS nor Sparc implement their FPU as stack based machines.

Now that we have narrowed it down to x86 the reason is obvious. Like many other things in computing it boils down to historical reasons (some call it hysterical raisins because the real reason does not really make sense).

The historical reason is that the x86 architecture did not have an FPU. Now, I know you'll say "but look at the Pentiums!". Yes they had FPUs but the original 8086 that IBM chose to build their PC around did not have an FPU - it was a strictly integer machine like lots of low end microcontrollers are these days.

That wasn't too much of a problem because it was mainly intended to be low end terminals and text processors. But its cheapness and popularity suddenly saw it being used in scientific and engineering applications. So people came up with add-on expansion cards with an FPU chip to speed things up. The most popular of these cards happen to use a stack based chip which was also manufactured by Intel. This small fact is what made it easier for Intel to later integrate the chip into future generations of CPUs.

At this point Intel could still have designed an instruction set that wasn't based on the add-on chip. But two things happened. Lots of apps, mostly games and spreadsheets, started using the add-on FPU and these apps became very, very popular. Also other chip vendors saw what was happening in the PC market and wanted in on the action. So, forced by backwards compatibility and needing to add this feature quickly Intel did the most sensible thing (in terms of business management, not necessarily in terms of engineering): they simply included the co-processor chip into their next version of x86 so that the marketing department could say they have an FPU.

Long story short: hysterical raisins!