There's a very good random library as part of the Open Source VHDL Verification Methodology here. There is a description and download link here.
http://www.synthworks.com/blog/osvvm/
It allows you to randomise much more than just a simple uniform distribution of floating point numbers. As well as isolating you from the state storage problem you have noted.
Regarding your specifics:
As I take it from the uniform function description, I should pass the two seeds from outside the function f because they are modified by the uniform function for the next call to uniform.
Yes, you should. Like this:
PROCESS
VARIABLE seed1, seed2: positive; -- Seed and state values for random generator
VARIABLE rand: real; -- Random real-number value in range 0 to 1.0
BEGIN
UNIFORM(seed1, seed2, rand);
So in your case, you'll have to pass those "state" variables into (and out of) your function too - which in practice means it has to be a procedure.
Or use the OSVVM library linked above which allows you to have a shared variable of protected type, which you can use from a variety of places. This keeps its own state "inside" the protected type.