Synplify prunes my register when I use to_integer to access a Constant Array. (VHDL)

Question

    Data_Out_SDa : process (SCl, IntReset) is
        variable IntSDa : std_logic;        -- Internal Sda
        begin  -- process Data_Out_SDa
        if IntReset = '0' then              -- asynchronous reset (active high)
           IntSDa := 'Z';
        elsif SCl'event and SCl = '0' then  -- falling clock edge
              IntSDa := DataBuffer(to_integer(unsigned(AddrReg)));
        end if;
        SDa <= IntSDa;
    end process Data_Out_SDa;

DataBuffer is a 121 bit constant std_logic_vector. Sda is an output port

The code synthesizes fine. But I get a warning Pruning Register IntSda, (CL169) and a warning Optimizing register bit IntSda to a constant 0 (Cl190)

For some reason the synthesize tool is interpreting that IntSda will always be 0. Note IntReset is an input. AddrReg is the output from a counter which changes value on the rising clock edge of SCl. The counter synthesizes fine and I have tested it on an FPGA and seen the output using a logic Analyzer. I'm at a loss for why this is happening. I could put a keep preserve, but I think that is a stop gap measure and no replacement for understanding the root cause.

Answer 1

You'll struggle to get Zs out that way. The synthesizer is probably treating them as '0's :)

I suggest you use 1s and 0s in the DataBuffer array and then drive SDa outside the process like this:

SDa <= '0' when IntSDa = '0' else 'Z';