Systemverilog random bit vector

Question

i'm using system-verilog and I want to randomize a bit vector with size of 100.
But i want that only 10 cells will get value of 1. I tried to use countones() in constraint but its not possible.

so i'm out of ides.

Thanks for any help!

Answer 1

I tried this code out and it works in Incisve:

package some_package;

class some_class;
  rand bit[99:0] vec;

  constraint just_10_ones {
    $countones(vec) == 10;
  }
endclass

endpackage


module top;

  import some_package::*;

  initial begin
    static some_class obj = new();
    obj.randomize();
    $display("vec = %b", obj.vec);
  end

endmodule

From what I remember, some vendors didn't support such constraints in the past, where a random variable is used as an input to a method. If they did support it, the value of the variable at the time of starting the randomize() was used for the input but this constraint did not affect its end value.