Clarification on interplay between cache line size and read/write sizes

Question

Say that you have cache lines with the size of 64 bytes and a set-associative or directly mapped cache. Let's also say that the word size is 8 bytes.

According to my understanding, we use a number of the most significant bits of a memory address in order to determine where in the cache to place the data. Am I correct in believing that, if I want load data starting from, for example, address 30, then all data starting from address 0 to 63 will be loaded into a cache line? Or will all data from address 30 to 93 be loaded?

If the former is the case, I assume that, if an instruction to load 16 bytes from address, say, 60, then this forces us to load two 64 byte cache lines (one line 0-63 and another 64-127). Is that correct or have I misunderstood something? Also, is this something that often occurs or are there reasons for why that isn't the case?