This is not a question of what the TLBs allow, but rather of what the architecture allows. The architecture says that you can mix small (4k), large (2M) and huge (1G) pages in the same page hierarchy, by setting the PS
bit in the page directory entry at the appropriate level.
Not all levels of TLBs will necessarily be able to cache pages of all sizes, but that shouldn't stop you from mixing pages if you so wish.
Now, there's nothing in the x86 pipe before the MMU that should actually require data about the page size. That is all encoded in the page hierarchy itself.
Regarding page splits, if you have a page boundary at address x
, and you have a memory access that starts at x - 1
that is more than 1 byte wide, it'll access both pages. This will work even if the two pages are different sizes.