ARM CPU Mode SVC Instruction

Question

This is the starting code of bootloader for ARM and configure the CPU into svc mode:

1)    mrs r0, cpsr
2)    bic r0, r0, #0x1F
3)    orr r0, r0, #0xD3
4)    msr cpsr, r0

and my question is why must we use the first instruction "msr r0, cpsr"? I mean can't we just use 2) 3) to obtain 0xD3 and write to cpsr directly? 1) serves to what exactly?

Answer 1

CPSR contains more state then just cpu mode.

For example it contains State bit telling whether CPU is executing in ARM or Thumb mode. Writing to CPSR without preserving other states would most likely put cpu into an undefined state. Because of this you always do a read-modify-write.

In most of the documents from ARM it is also stated the importance of keeping state of reserved bits for future compatibility.

To maintain compatibility with future ARM processors, and as good practice, you are strongly advised to use a read-modify-write strategy when you change the CPSR.

Answer 2

Well in fact instruction 2 and 3 manipulates bits 7,6 and 4,3,2,1,0:

I is set (Masking IRQs) F is set (Masking FIQs)

MODE is set to 0b10011

Left bits are unchanged, thanks to the read-modify-write sequence (which by the way answers your question about usefulness of instruction 1)