The reason the different simulator give different results likely has to do with what it constitutes as true
for the solver. Using the following example:
rand bit [1:0] example;
rand bit one_beat;
constraint example_c { if(!one_beat) example; }
In this case example
has the same randomization width as { addr[5:0] == 0, len == 15 }
. Depending on the simulator the above constraint may infer example==2'b1
or example!=2'b0
or example>2'b0
(different results with signed and unsigned) . If one_beat
wasn't an one-bit value, the same issue would be true for want counts as true for the if()
statement.
If the OR option is intended, a better way to write the constraint would be:
if (!one_beat) ( addr[5:0] == 0 || len == 15 );
or
if (!one_beat) { addr[5:0] == 0, len == 15 } != 0; // or '>0', '>=1', etc
There is a good change the creator of the constraint intended both constraints to be true when if(!one_beat)
. In this case the follow would be better constraint options:
if (!one_beat) { addr[5:0] == 0; len == 15; } // note the semicolon positions
or
if (!one_beat) ( addr[5:0] == 0 && len == 15 );
Also note that with the given SSCCE, one_beat
has a very low probability of being 1'b0
because the solver is trying to find a legal condition for one_beat
, addr
and len
in parallel with equal priority.
- When
addr[5:0]==0 || len==15
its probability is1/(1+2**6) + 1/(1+2**32)
- When
addr[5:0]==0 && len==15
its probability is1/(1+2**(6+32))
If this is not intend, then add another constraint such as one_beat dist { ... };
or sovle one_beat before addr,len;
constraints
IEEE Std 1800-2012 § 18.5 Constrained random value generationdist {...}
IEEE Std 1800-2012 § 18.5.4 Distributionsolve ... before ...
IEEE Std 1800-2012 § 18.5.10 Variable ordering