So assuming you are talking about a standard 5-stage MIPS pipeline, the load instruction writes the destination register at the same time as any other instruction would - at the end of the writeback stage. So if we look at the following example:
cycle 0 1 2 3 4 5 6 7 8 LD R1, [MEM] F | D | X | M | WB | ADDi R1, R1, #5 | F | D | D | D | D | X | M | WB
Assuming there is no data-forwarding (or bypassing) in the pipeline, the loaded data will only become available the cycle after writeback. In case you have forwarding around the register file, it will look like this:
cycle 0 1 2 3 4 5 6 7 LD R1, [MEM] F | D | X | M | WB | ADDi R1, R1, #5 | F | D | D | D | X | M | WB
As you can see, in cycle 4, where data was already loaded and sitting in the pipeline register between Mem and Wb stages, it was bypassed back to the Decode stage and written into the register file and into the pipeline register between the Decode and eXecute stages simultaneously.
With super aggressive bypassing you could get the data even one cycle earlier.
But in all of these examples, the LD instruction is still writing the destination register R1 at the end of Writeback stage.