Do all MIPS Instructions take 5 cycles to complete

Question

As there are some instructions that are being used in MIPS Architecture, which doesn't require all 5 cycles for its successful completion, like the store instruction doesn't need to use 5th stage. So does the instruction will also pass through the stage or does it skip the stage?

Answer 1

In a multi-cycle CPU the each of the instructions can take a differing number of instructions.

As you suggested, one of the ways that this can occur is by having an instruction "skip" a pipe-line stage. This is accomplished by having a control unit direct execution of the CPU by having separate execution paths for necessary instructions.

Maybe take a look here for some further information on how a MIPS multi-cycle machine might be implemented.

Generally speaking though, you should take these sorts of explanations with a grain of salt. The sort of machine architecture we learn as non-hardware experts is often quite quaint in comparison to how complicated these things have gotten to the extent that our understandings are often several decades out of date.