Inaktivität Kill-Switch für Systemverilog Testbench Simulation (VCS)

Question

hi und danke dafür, dies zu sehen.

Ich überlegte über die Idee eines Inaktivität Killswitchs für die Systemversiogsimulation.

Gibt es eine Möglichkeit, in der eine längere (programmierbare) Dauer der Inaktivität beim Ausführen von "SIMV" ein internes Ereignis auslösen kann, um '$ ende' anzurufen?Oder ist es möglich, den VCS-Befehl zu verwenden?

lässt Brainstorming.Und lass es mich wissen, wenn etwas unklar ist.

rrs

Answer 1

In VHDL I use a resolved signal.

Each process that generates or analyses data writes 0 to that signal while it is working. Once it is in a state for the simulation to finish, it writes 1.

Only when all processes are happy does the signal change state to a 1 (it's either X or 0 the rest of the time).

The clock generation processes monitor this signal and when it becomes 1 they stop producing clock pulses; no further transitions are scheduled, and the simulator knows to stop.

Presumably Verilog can do something similar.

Answer 2

Inside the chip design companies that I've worked for, this is called a "quiescent check", but I'm not sure if that's an industry standard name. You implement "instrumentation code" that checks that the system has acheived quiescence. V̶e̶r̶i̶s̶i̶t̶y̶'̶s̶ Cadence's Specman-e tool does this quite elegantly with its objection to end of test mechanism (raise_objection(MAIN_TEST_DONE)/drop_objection(MAIN_TEST_DONE)). Essentially, monitors throughout throughout the system "raise" an objection at the beginning of simulation ( i.e. increment the counter), then when the simulation runs, they determine that their piece of the DUT is quiescent and they "lower" the objection (i.e. decrement this global counter). When there are no more objections to ending the test, (i.e. the global counter is 0), then $finish is called. The monitors can raise and lower objections throughout the test, but if and when the counter ever reaches 0, the test is $finish'd.

Universal Verification Methodology (UVM) took up this methodology from Specman and it is described here in their UVM Reference Manual. UVM is implemented with Verilog first and foremost, so you could definitely use their freely available library to implement "quiescent checking". Cadence's Specman UVM reference manual also describes this mechanism at http://support.cadence.com . Unfortunately, Cadence requires that you be a customer before they'll show you their documents and thus you must use a non-Google search engine to find what you want. It's a bit of a pain.