Why does /proc/cpuinfo differ from the Intel Specification? [closed]

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when I run: cat /proc/cpuinfo on my machine I get the following output:

mk527@node5: ~
$ cat /proc/cpuinfo 
processor   : 0
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 0
siblings    : 4
core id     : 0
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4662.55
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

processor   : 1
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 1
siblings    : 4
core id     : 0
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4655.40
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

processor   : 2
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 0
siblings    : 4
core id     : 1
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4655.15
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

processor   : 3
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 1
siblings    : 4
core id     : 1
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4656.47
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

processor   : 4
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 0
siblings    : 4
core id     : 2
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4655.36
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

processor   : 5
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 1
siblings    : 4
core id     : 2
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4655.39
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

processor   : 6
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 0
siblings    : 4
core id     : 3
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4653.23
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

processor   : 7
vendor_id   : GenuineIntel
cpu family  : 6
model       : 15
model name  : Intel(R) Xeon(R) CPU           E5345  @ 2.33GHz
stepping    : 7
cpu MHz     : 2327.551
cache size  : 4096 KB
physical id : 1
siblings    : 4
core id     : 3
cpu cores   : 4
fpu     : yes
fpu_exception   : yes
cpuid level : 10
wp      : yes
flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr dca lahf_lm
bogomips    : 4655.34
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

I looked up the intel model number E5345, here's the link: http://ark.intel.com/products/28032/Intel-Xeon-Processor-E5345-%288M-Cache-2_33-GHz-1333-MHz-FSB%29 I see that L2 cache for this processor should be 8MB but according to the above I am only seeing 4MB. What is the reason for this discrepancy?

Thanks in advance!

Answer 1

They are measuring two different things. When Intel says a CPU has 8MB of L2 cache, that means there's a total of 8MB of L2 cache memory in the package.

Say the CPU has four cores. Each core could have 2MB of L2 cache memory, totaling 8MB in the package. Or all four cores could share a single 8MB L2 cache, still giving each core an 8MB L2 cache, though it's shared. Or there could be two 4MB caches, each shared by two cores. This would give each core a 4MB L2 cache.

The cpuinfo file reports per core, not per package. So the relationship between the package L2 cache and the cache reported there will depend on the details of the cache implementation.