Shadow registers -- arm

Question

Shadow registers are used to reduce interrupt latency.

Arm has 15 registers, then where are these shadow registers stored?

Is the term "shadow registers" related to banked and non banked registers?

Answer 1

ARM technical documents don't mention shadow specifically, so it is kinda hard to relate it to ARM.

However from a comparision of ARM to MIPS architecture point of view:

The MIPS architecture supports the implementation of multiple “shadow” banks of registers. This allows more efficient context-switching operations but the fact that this feature is not commonly or consistently implemented on MIPS-based devices makes it of limited use. Consequently, few compilers or operating systems make use of it.

In this context "shadow registers" are more kinda stand free thing - they can be utilized for many things, while banked registers are for clearly separated execution modes.

Answer 2

arm has many more than 15 registers, which 15 out of that bank of registers you can access is mode dependent. the arm architectural reference manual found at infocenter.arm.com (just get the ARMv5 one which covers the traditional arm arch) shows the list of registers and what mode you need to be in to access them.

ARM does not use the term shadow registers, but fiq mode is similar to what you are asking as you dont have to preserve many or any registers from the interrupted task. ARM goes further to have multiple stacks, etc depending on mode.