From the looks of it, is is doing what you intended but with optimizations. The clkCount is declared as an integer or 32 bits, but you have it reset to 0 once it hits majority value or 3, which equates to "11" or 2 bits. So therefore clkCount(31 downto 2) will get optimized out since it's always 0.
I would assume that Sum should get optimized down, but the synthesis tool may not notice the coupling that it could get optimized as well.
I'm not a big fan of hard-coded values and you could probably expand this with generics to make it more customizable if you instantiate multiple Clock counters.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL;
entity ClockCounter is
generic (
totalBitWidth : integer := 4;
majorityValue : integer := 3);
port(
clk : in std_logic;
input : in std_logic;
enable : in std_logic;
output : out std_logic := '0';
bitReady : out std_logic := '0';
countError : out std_logic := '0');
end ClockCounter;
architecture Behavioral of ClockCounter is
begin
-- Process for recognizing a single input value from a clock cycle -- wide input signal
majority_proc : process(clk, input, enable)
variable clkCount : integer := 0;
variable Sum : integer := 0;
begin
if rising_edge(clk) and enable = '1' then
-- Reset bitReady after one clock cycle
bitReady <= '0';
-- Check the input value and add it to the Sum variable
if input = '1' then
Sum := Sum + 1;
else
Sum := Sum + 0;
end if;
-- Increment the clock counter variable
clkCount := clkCount + 1;
-- Check if the clock count has reached the specified number of cycles
if clkCount >= totalBitWidth then
-- Determine if the Sum variable has met the threshold for
-- value of 1, set the output accordingly
if Sum >= majorityValue then
output <= '1';
else
output <= '0';
end if;
-- This checks if the value for all clock cycles was the same and
-- sets an error flag if not
if Sum = totalBitWidth or Sum = 0 then
countError <= '0';
else
countError <= '1';
end if;
-- Reset the clock counter and sum value
clkCount := 0;
Sum := 0;
-- Set the bit counter high to alert other midules that a new bit
-- has been received
bitReady <= '1';
end if;
elsif enable = '0' then
clkCount := 0;
Sum := 0;
end if;
end process;
end Behavioral;