why logical right shift and arithmetic right shift have a shift range of 1- 32 [duplicate]

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Why different ranges of permitted shift values for ARM LSL vs LSR? (1 answer)

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I have seen that Logical left shift can do a shift form 1-31 bits .Arithmetic right and logical right shift take 1 -32 as shift amount . Why the difference between the right and left shifts?

Answer 1

It has to do with the special meanings of certain shift operations. From DDI 0029E (the ARM7TDMI datasheet):

LSL #0 is a special case, where the shifter carry out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand.
....
The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified.

In other words, the processor designers assigned a special meaning to LSL #0, which also means that there's no possible encoding for LSL #32 since shift amounts of 1..31 are interpreted as-is and 0 has its special meaning. LSR #0 and ASR #0 will be converted to LSL #0 by the assembler since they have the same meaning, which means that the machine code encodings for LSR #0 and ASR #0 were free to use for something else; so they made a shift amount of zero be interpreted as 32 for LSR/ASR.

Answer 2

I believe this has to do with the ARM barrel shifter. Basically the ARM architecture has no real shift instruction. Instead it gives you the possibility to do shifts as part of other instructions, using the barrel shifter.

Before processing the instructions that accept a shift the processor will check if a shift was specified. If it was not the default shift applied is LSL #0.

Now the amount by which the register will be shifted is specified either on a 5-bit field in the instruction, or on the bottom byte of a register. Using the 5-bit field, however, has no extra overhead, while using a register requires an extra cycle.

5 bits gives you 32 different values. Since we need to have a 0 value when we don't want to apply any shifts the possible values of LSL range from 0-31, while LSR and ASR have a range of 1-32 because you will never need to do a LSR #0 or ASR #0.

As for LSR #32 or ASR #32, those can be useful if you want to set the register either with zeroes or ones and know what the last bit to be shifted was, since it will be moved to the carry bit.