ISR,DPCs and Processor cache

Question

I read here that ISRs and DPCs can dirty the processor cache. Can anyone explain how?

Answer 1

ISRs and DPCs can preempt the currently running code due to higher priority of their execution level. Once preemption is done, the ISR/DPC code begins to execute. Memory addressing is a very basic operation and it will be required almost certainly. Once memory access is requested, a cache line might be replaced.

To summarize the above - ISRs and DPCs disrupt the stable state and perform out-of-order operations due to their higher priority. Often the execution will require different memory than currently cached (because it's not part of the logic that was executing before the preemption), resulting in pollution with respect to the code that was executing prior to the interrupt.