test bench multiple architectures

Question

sorry I'm new to this website, but I have been searching for answers for almost 2 days straight.

I am new to vhdl, and an assignment has asked to make a simple 16-bit ALU. This ALU needs 2 architectures: the behavioral, as well as the RTL design. I have the code for that complete as far as I am concerned.

What I cannot figure out is how to write a test bench that will allow me to run the simulation for both architectures in modelsim. I have both files (test bench and ALU) which compile fine, however I get errors in the simulation saying that "uninitialized inout port has no driver"

I'm not sure what code to show for this problem so I'll just show you the beginning of my TB.

    LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

   signal Clk,Res : std_logic := '0';
   signal A,B : signed(15 downto 0) := (others => '0');
   signal R1, R2 : signed(31 downto 0) := (others => '0');
   signal Op : unsigned(2 downto 0) := (others => '0');
   constant Clk_period : time := 10 ns;

component ALU_16_First
port(A, B: signed(15 downto 0):=(others => '0'); R: inout signed(31 downto 0):= (others => '0'); Op: in unsigned(2 downto 0) := (others => '0'); Clk, Res: Std_logic);
end component ALU_16_First;

component ALU_16_RTL
port(A, B: in signed(15 downto 0):= (others => '0');
     R: inout signed(31 downto 0):= (others => '0'); Op: in unsigned(2 downto 0) := (others => '0'); Clk, Res: Std_logic);
end component ALU_16_RTL;

for ALU_Behaviorial: ALU_16_First use entity work.simple_alu(Behavioral);
for ALU_RTL: ALU_16_RTL use entity work.simple_alu(RTL);

BEGIN

    -- Instantiate the Unit Under Test (UUT)

   ALU_Behaviorial : ALU_16_First  PORT MAP (
          A,
          B,
          R1,
          Op,
          Clk,
          Res
        );

    ALU_RTL: ALU_16_RTL PORT MAP (
          A,
          B,
          R2,
          Op,
          Clk,
          Res
        );

I'm basically desperate to get this done on time.

Thanks.

Answer 1

It looks fine other than the R port being inout (as Russell noted). If for some reason you need the R port to be bi-directional, make sure to assign it to 'Z' during appropriate times in the testbench:

testProc : process
begin
  ...
  R <= (others => 'Z') ; 

In the future, you can save your self some time by using a direct entity instantiation in place of the component declaration, configuration specification, and component instantiation:

 ALU_Behaviorial : use work.simple_alu(Behavioral)  
 PORT MAP (
      A => A_tb,
      B => B_tb,
      R => R1_tb,
      Op => Op_tb,
      Clk => Clk_tb,
      Res => Res_tb
    );

If you stay with component declaration, there is no need to create separate component names for each of the models. It is your configuration specification that is associating the architecture name with the entity.

I recommend that you forget about configuration specifications and use direct entity instantiation for simple cases and configuration declarations for more complex cases.

Answer 2

I recommend using explicit port mapping to make it completely clear what's going on in your component instantiations. So for example:

   ALU_Behaviorial : ALU_16_First  PORT MAP (
      A => A_tb,
      B => B_tb,
      R1 => R1_tb,
      Op => Op_tb,
      Clk => Clk_tb,
      Res => Res_tb
    );

_tb signals are your test bench signals. Now, ensure that your inputs to your components (A_tb, B_tb, R1_tb, Op_tb, Clk_tb, Res_tb) are being driven by your test bench architecture. Where is your test bench driving these inputs?

Also, Is there a good reason why you chose to make R1 an "inout"? Could you just make it an out? It might be a bit easier for you.