what's the difference in position declaring variable in xilinx?

Question

I'm a beginner writing verilog via xilinx.

I have learned port declarations must be like below

module mealy(
  nReset,
  clk,
  in,
  out
);

  input  nReset;
  input  clk;
  input  in;
  output out;
endmodule

When I use xilinx, it has default option to set variable, it appears like this:

module mealy(
  input  nReset,
  input  clk,
  input  in,
  output out
);

endmodule

Sometimes, when I use second way, it generates an error. What is the difference between two styles?

---

A secondary issue, when declaring outputs as regs the first style works correctly ie

module mealy(
  in,
  out
 );

  output out;
  input  in;
  reg    out;
endmodule

When using the second style, It generates an error stating that you can't declare twice.

module mealy(
  input  in,
  output out
);
  reg out;
endmodule

What is the matter? I am just beginner I don't know exactly why I must declare 'reg'.

Answer 1

Verilog 1995 often referred to as verilog-95 (IEEE 1364-1995), use to have port declarations separated from directions and separate again from reg types.

Since Verilog 2001 (IEEE 1364-2001) the more compact version can be used.

If your tools are only 95 standard compliant they will error on code intended for 2001 or later.

When using the new port declaration, including direction you should also declare type if not a wire.

module mealy(
  input  in,              // Inputs are implicitly wires (reg would not make sense)
  output     [1:0] out_x, // 2 bit wire type as output
  output reg [1:0] out_y  // 2 Bit reg  type as output
);
endmodule

The difference between reg and wire types should be looked up, basically it is a simulation optimisation. If using SystemVerilog they can both be replaced with a logic type.

Wires are driven by ports, or assign statements. regs are assigned inside always or initial blocks. reg does NOT imply flip-flop.