I understand the fundamentals of verilog, but test bench just won't make sense

Question

Half Adder:

`timescale = 1ns/100ps //timescale ratio //actual HDL

module half_add(a,b,sum, carry);
  input a,b;
  output sum, carry;

  wire sum, carry;

  and(sum,a,b);
  xor(carry,a,b);
endmodule

Test bench:

module half_addTB;
reg a,b;
wire carry, sum;

//instantiation
half_add half_add1(
.a(a),.b(b),.carry(carry),.sum(sum));

 //port assignments with 10ns delays
initial begin
  #10 a = 0; b= 0;
  #10 b = 1;
  #10 a = 1;
  #10 b = 0;
end

endmodule

Code compiles fine...but when I try to simulate it, all my values are in a z state....I don't understand why..

Answer 1

You cannot drive inputs to the module from within the module.

Just instantiate your "half_add" module in another module/program (e.g. "half_add_tb") which doesn't have any inputs. then add two local regs "a" and "b", and drive those from an initial block like the one you wrote - but in the "half_add_tb" module instead.

Then just wire up the inputs "a" and "b" of the "half_add" instance to the local "a" and "b" regs.

Answer 2

You need to instantiate your design in a testharness then drive the inputs.

//Half Adder
module half_add(a, b, sum, carry);
  input  a,b;
  output sum, carry;
  wire   sum, carry; //Outputs are wires by default this is not required

  and(sum,  a, b);
  xor(carry,a, b);
endmodule

module testharness();
 //create test signals
 reg a; //1 bit reg (regs driven from always and initial blocks)
 reg b;
 wire sum; // 1 bit wires for outputs to drive
 wire carry;

  //instantiate DUT (Device under test)
  half_add half_add_1(
    .a     ( a    ), 
    .b     ( b    ), 
    .sum   ( sum  ), 
    .carry ( carry)
  );

  //begin testbench
  initial begin 
    #100 $finish;
  end

  initial begin
    #10 a = 0; b= 0;
    #10 b = 1;
    #10 a = 1;
    #10 b = 0;
  end

endmodule

NB: if your simulator supports verilog-2001 your port lists can be easier to read and more compact:

//Half Adder
module half_add(
  input       a, 
  input       b,
  output wire sum,  
  output wire carry
//for regs : 
//    output reg [WIDTH-1:0] out_reg
//multi-bit wires : 
//    output     [WIDTH-1:0] out_wire
);

  and(sum,  a, b);
  xor(carry,a, b);
endmodule