Is it possible to compile multiple target files using CC compiler?

Question

I am using Minix 2.0.4 so I can't use gcc. I want to use one make file to compile multiple C programs, with multiple targets.

Here is the current state of my Makefile

CFLAGS  = -D_POSIX_SOURCE
LDFLAGS =
CC      = cc
LD      = cc

PROG    = prog1 prog2 
OBJS    = prog1.o prog2.o

$(PROG): $(OBJS)
         $(LD) $(LDFLAGS) $(OBJS) -o $(PROG)

clean:
         rm -rf $(PROG) $(OBJS)

However, when I try and use my makefile like this is get an error that says "prog2: can't compile, not transformation applies". Any ideas on what I'm doing wrong?

Answer 1

Split it up this way:

PROG1 = test 
PROG2 = test2
OBJ1 = test.o
OBJ2 = test2.o


all: $(PROG1) $(PROG2)

$(PROG1): $(OBJ1) 
          $(LD) $(LDFLAGS) $(OBJ1) -o $(PROG1)
$(PROG2): $(OBJ2) 
          $(LD) $(LDFLAGS) $(OBJ2) -o $(PROG2)

etc

If all that subsitution makes you nervous, you can more simply say

all: test test1

test: test.o
      $(LD) $(LDFLAGS) test.o -o test
test2: test2.o
      $(LD) $(LDFLAGS) test2.o -o test2

And remove this from the beginning:

PROG1 = test 
PROG2 = test2
OBJ1 = test.o
OBJ2 = test2.o

There are other shortcuts, but this more specific and obvious.

Answer 2

To do exactly and only what you are asking, you do not need any Makefile at all. GNU Make has "built-in rules" for what you want:

> ls Makefile
ls: cannot access Makefile: No such file or directory
> make prog1 prog2
cc   prog1.o   -o prog1
cc   prog2.o   -o prog2

By the way, in general,

> make prog1 prog2

is subtly different, from having an additional all: prog1 prog2 target, and doing

> make all

The former makes the first target and then the second, completely independently, as if in two successive invocations. The second, makes them in one invocation: probably faster for large makefiles, possibly in parallel if invoked with -j ..., and possibly with different messages output.