Question

Is it possible to synthesize an enable signal that asserts on a cycle if and only if an interface method/task is invoked on that cycle? Something similar to the following is desired:

interface RAM (logic clk);
  logic enable;
  // ...

  always_ff @(posedge clk) enable = 0;

  task Read(input address_t address);
    enable = 1;
    // ...
  endtask

  //...

  modport server(input clk, input enable, ...);
  modport client(input clk, export Read, ...);
endinterface

Clearly the above is illegal. The only idea I've had is to save the previous state, compare if the current and previous assignment are the same or not in the always_ff, and negate in the task invocation. That doesn't seem practical though - it's very specific and thus less likely to be optimized away during P&R. What I really need is a logic element with the semantics that when assign to it takes the value assigned, otherwise it goes to a default value.

Was it helpful?

Solution

You can only write to a signal from a single process. But you can write the the same variable multiple times from the same process, last write wins. So you can do

always_ff @(posedge clk) 
    begin 
    enable <= 0;
    case(opcode)
    READ_OP: Read(...);
    WRITE_OP: Write(...);
    endcase

Note that you must always use NBA <= to assign to enable inside your tasks (and use void functions instead of tasks if Read/Write do not consume time.

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