Distinguish between simulation and HDL code generation in simulink

Question

I am building a model using Simulink / Matlab Embedded Coder which is then converted to VHDL through HDL Coder. It should behave slightly different in simulation versus HDL, in particular concerning debug-output.

Is there a programmatic way to distinguish which target is selected? This should preferably not need a manual switch such as "DEBUG = 1;" and ensure that disabled code or sub-models will not be synthesized at all. If the different "accelerator" modes could also be distinguished, that would be a plus.

Update: Such a switch should come into effect before the HDL code is auto-generated, since I want to avoid to manually touch generated code.

Solution: I found a solution that partially answers my question: EnvironmentController offers such a switch in Simulink. Maybe there's also an Embedded-Matlab-only way?

Answer 1

When you have MATLAB code in your Simulink model you can use coder.target to identify the target. You can differentiate between "C" code generation and "HDL" code generation using this.

coder.target("HDL") would be true when you are generating HDL.

Doc for this is at http://www.mathworks.com/help/coder/ref/coder.target.html