Z80 Instruction Register Size

Question

I am writing a Z80 emulator and I am confused as to how large the instruction register is.

In the Z80 manual it states that the instructions are from 1 to 4 bytes long, am I given to assume that the Z80 has a 32Bit instruction register? If not then how does it execute instructions like this?

Answer 1

There's no instruction register, and you don't fetch the entire instruction at once. Instead, you fetch it piece-by-piece.

Let's walk through your example instruction:

• Your emulator begins by fetching one byte from the current PC, and increments PC.
• It looks at the byte, which is 0xDD, and the emulator knows that this is the "IX instruction prefix" (because you know this, and therefore have programmed your emulator to know it). Your emulator then fetches another byte to get the actual opcode.
• The opcode byte is 0x36, and your emulator knows 0x36 prefixed by 0xDD is LD (IX+d),n with the encoding 0xDD 0x36 dd nn.
• Your emulator then fetches the dd and nn bytes, writes nn to (IX+dd), increments the cycle counter and proceeds to the next instruction.

If you want to write a cycle-accurate emulator things get a bit more complicated, but I wouldn't recommend that if you're a beginner when it comes to emulation.

Answer 2

All it says is that instructions can be 1-4 bytes long. This does not automatically allow an assumption about an instruction register. It says that it is M Cycles: 5. That makes it clear it needs 2 bytes to get the instruction (M Cycles 1 and 2). Then it reads the next 1 byte (M Cycle 3) adds it to the IX register and then it reads another byte (M Cylce 4) which which it then writes to the computed address (M Cycle 5).

Answer 3

Actually the IR register exists, but is not accesible by the programmer. Check the Rodnay Zaks book How To Program The Z80 (page 56). It clearly explains how 1-byte instructions are fetched & decoded, however I still don't get how 2-byte, 3-byte or 4-byte instructions are treated. It would be nice to have a step by step example showing how a 2, 3 or 4 byte instruction is processed using the IR register.