Crossing clock domains within a device

Question

I am working on designing a Pilot Insertion module in VHDL to be implemented on an FPGA which is part of an OFDM system. For every 48 words coming from the modulation components, the pilot insertion will add pilot tones and NULLs to fill the remaining channels of a 64 channel IFFT. I am trying to achieve streaming operation of this system so it will constantly produce the 64 samples for serial input to the IFFT with a fixed latency.

My approach is to use two-port RAM, one port for receiving the modulated words and the other port for writing out to the IFFT. Each port is running on an independent clock, and outside the device I have a 4/3 clock divider so the output receives 64 clocks for every 48 clocks to the input.

My question is whether this is a valid design strategy, and what types of pitfalls I should be aware of. Also, I would appreciate if anyone has alternative suggestions for how I can accomplish this.

Thanks, technocratic

Answer 1

So clock that drives the 48 logic is derived from the clock that drives the 64 logic? If this is the case, then you know that your clocks have a guaranteed relationship and you don't need to worry about clock drift. This makes your job easier.

Is there a reason that you need a RAM? Do you need to be able to access the value of the RAM out of order? I would suggest using a FIFO if you can, it will make your job easier. You won't need to keep track of read/write addresses.

Just make sure that you isolate the two clock domains. I would recommend putting all logic that writes to the RAM or FIFO in one file, and putting all logic that reads to the RAM or FIFO in another file. The RAM/FIFO can exist at the TOP level that instantiates the two lower level components.

This will help you ensure no clock domains are being crossed in strange places. The RAM/FIFO should be your ONLY interface between the two domains.