why can MemoryBarrier be implemented as a call to xchg?

Question

on msdn http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208(v=vs.85).aspx, MemoryBarrier is implemented as a call to xchg.

// x86

FORCEINLINE
VOID
MemoryBarrier (
    VOID
    )
{
    LONG Barrier;
    __asm {
        xchg Barrier, eax
    }
}

I can't find some material in "Software Developer's Manual". please tell me the reason.

Answer 1

From Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3: "System Programming Guide"

8.2.5 "Strengthening or Weakening the Memory-Ordering Model"

Synchronization mechanisms in multiple-processor systems may depend upon a strong memory-ordering model. Here, a program can use a locking instruction such as the XCHG instruction or the LOCK prefix to ensure that a read-modify-write operation on memory is carried out atomically. Locking operations typically operate like I/O operations in that they wait for all previous instructions to complete and for all buffered writes to drain to memory (see Section 8.1.2, “Bus Locking”).

And from 8.1.2:

Locked operations are atomic with respect to all other memory operations and all externally visible events. Only instruction fetch and page table accesses can pass locked instructions. Locked instructions can be used to synchronize data written by one processor and read by another processor.

For the P6 family processors, locked operations serialize all outstanding load and store operations (that is, wait for them to complete). This rule is also true for the Pentium 4 and Intel Xeon processors, with one exception. Load operations that reference weakly ordered memory types (such as the WC memory type) may not be serialized.

Answer 2

Two things happen here:

1. The compiler is given an opaque block to insert into the output instruction stream. As it does not know which data is accessed inside the block, it cannot reorder the other statements around it.

2. The xchg instruction performs an atomic read-modify-write operation, which requires ordering on the memory bus, so the CPU enforces a memory barrier.