Verilog: task using case not choosing the correct case

Question

I have the follow task, but some how when I use the task, it doesn't give me the correct digit output, I have tried not using the task, and it give me the correct output. Can any one see if I have anything wrong?

For example when display(17,hex3), both display all off, instead of all off and digit '1'.

I'm using 7-segment for the 4 digit, hex[6:0], 1 is off.

output reg [6:0] hex3, hex2, hex1, hex0 

task display;
  input  [5:0] num;
  output       hex;
  reg          hex;
    begin
      case(num) // 6543210
        if(hex==hex3) begin
           0:hex3 =7'b1000000; //0          
           1:hex3 =7'b1111001; //1          
           2:hex3 =7'b0100100; //2          
           3:hex3 =7'b0110000; //3          
           4:hex3 =7'b0011001; //4          
           5:hex3 =7'b0010010; //5          
           6:hex3 =7'b0000010; //6
           7:hex3 =7'b1111000; //7
           8:hex3 =7'b0000000; //8
           9:hex3 =7'b0011000; //9
          10:hex3 =7'b0001000; //A
          11:hex3 =7'b0000011; //b
          12:hex3 =7'b1000110; //C
          13:hex3 =7'b0100001; //d
          14:hex3 =7'b0000110; //E
          15:hex3 =7'b0000111; //F
          16:hex3 =7'b0010000; //g          
          17:hex3 =7'b1111111; //Off            
          18:hex3 =7'b0001001; //H
        endcase
      end
      else if(hex==hex2) begin
        case(num)
           0:hex3 =7'b1000000; //0          
           1:hex2 =7'b1111001; //1          
           2:hex2 =7'b0100100; //2          
           3:hex2 =7'b0110000; //3          
           4:hex2 =7'b0011001; //4          
           5:hex2 =7'b0010010; //5          
           6:hex2 =7'b0000010; //6
           7:hex2 =7'b1111000; //7
           8:hex2 =7'b0000000; //8
           9:hex2 =7'b0011000; //9
          10:hex2 =7'b0001000; //A
          11:hex2 =7'b0000011; //b
          12:hex2 =7'b1000110; //C
          13:hex2 =7'b0100001; //d
          14:hex2 =7'b0000110; //E
          15:hex2 =7'b0000111; //F
          16:hex2 =7'b0010000; //g          
          17:hex2 =7'b1111111; //Off            
          18:hex2 =7'b0001001; //H
        endcase
      end
   endtask          


   //final
   always @(*) begin
     if(init) begin
       display(17,hex3);
       display(1,hex2);     
     end
   end

Answer 1

input num;

The above code implies a 1 bit input. You need this to be wider, 4 bits to control 0 to F. If you need additional states such as OFF the you will need at least 5 bits.

you should probably add a default case as well may be to off, then you do not need to fully describe the unused states.

  //...
  default:  hex =7'b1111111;
endcase