Explanation on how this makefile works?

Question

I found a makefile here while reading about Auto-Tools.

I never used a makefile like this, I tried this myself.
The contents of makefile I wrote are:

all: HelloWorld

clean:
    rm -f HelloWorld *.o

The folder containing the makefile contains just one more file HelloWorld.c.

Running make was successful with following output:

$> make
cc     HelloWorld.c   -o HelloWorld

Now I tried experimenting, and in the makefile I renamed the target for all to HelloWorl. This time make failed with following error:

$> make
make: *** No rule to make target `HelloWorl', needed by `all'.  Stop.

Please explain this behaviour of make automatically searching and compiling the source.

My understanding is that it is making the source name from the target name by appending .c and compiles it using the default cc compiler.

Answer 1

Your understanding is mostly correct; this is one of the implicit rules. However, make actually compiles the file using the compiler in make's CC variable.