SystemVerilog macros not needing a ';' at the end of a line

Question

In SystemVerilog, it is not required to add a ';' at the end of a line. For example:

`uvm_do(pkt) 

I wonder why the compiler can handle this, but can't handle regular lines without the ';'.

Answer 1

SystemVerilog always requires semicolons at the end of a statement.

However, you need to look at the code expanded by the UVM macros. Most macros expand into code that looks like:

`define uvm_whatever \
    begin \
       some_code(); \
    end

If you were to type out the begin/end code manually, you would not need a semicolon after the end. Therefore, you do not need a semicolon at the end of the macro call.

Here is a quote from the UVM docs:

Macros represent text substitutions, not statements, so they should not be terminated with semi-colons.