Initializing a shift register

Question

I made a module for a shift register and am trying to initialize it by a variable value. But its not working

Here is the code

module shiftreg(dataOut,EN, in, CLK, Q,init);
   parameter n = 4; 
   input [n-1:0] init; //the initial value of the register
   input EN; input in; 
   input CLK; output [n-1:0] Q; output dataOut; reg dataOut;
   reg [n-1:0] Q;  //needs to be saved for future shifts.

   initial 
   begin
      Q=init; dataOut=init[0];
   end

   always @(posedge CLK) 
   begin 
      if (EN) 
      begin
         Q={in,Q[n-1:1]}; 
         dataOut=Q[0];
      end 
   end 
endmodule

Answer 1

init would need to be a content to work inside of an initial block and it would only work for RTL simulation and some FPGAs. Most synthesizers ignore initial blocks. A better approach is to add a bit to load. It is a good idea to out non-blocking assignments to registers. You can save a flop with dataOut by using an assign statement.

always @(posedge CLK) begin
  if (LOAD)  Q <= init;
  else if (EN)    Q <= {in,Q[n-1:1]}; 
end
assign dataOut = Q[0];