Build file (Rake or Make?) for building a few simple libraries with common options?

Question

So, I have a set of different libraries in C and C++ that I need to build with some common options. My current "template" makefile looks something like so:

#Change this for different MCUs. Standard includes atmega328
VARIANT = ../variants/standard 

HDRS=RedBot.h

OBJS=RedBot.o RedBotAccel.o RedBotMotor.o RedBotSensor.o


CPPFLAGS = -I../arduino/ -I./ -DF_CPU=16000000UL -Os -mmcu=atmega328p

CC=avr-gcc
CPP=avr-g++
AR=avr-ar


default: libredbot.a

libredbot.a:   ${OBJS}
    ${AR} crs libredbot.a $(OBJS)

.c.o: ${HDRS}
    ${CC} -I ${VARIANT} ${CFLAGS} -c $*.c

.cpp.o: ${HDRS}
    ${CPP} -I ${VARIANT} ${CPPFLAGS} -c $*.cpp

clean:
    rm -f ${OBJS} core a.out errs *.a

I place the makefile in the same folder as all the sources. However, this is ugly for a few reasons. For one, it's only a template. I have to duplicate this across about 15 libraries. And I need for the compilation options to be very easy to change across all libraries, because multiple targets is common. Currently, the best thing I can think of is making a root makefile with the options passed to each library makefile. However, I still have to keep track of all the files (the OBJS bit). And not all libraries are capable of being built on all targets.

Can someone point me either to a more comprehensive makefile, or possibly an example build file for something like Rake that could handle this?

Answer 1

I ended up writing my own little hacky thing with Ruby to get this done easily. You can draw inspiration from it here: https://github.com/Earlz/make-wiring/blob/master/build.rb

Basically, it consists of a "template" makefile that takes many environment variables. And the build.rb script just passes them off to the makefile without you having to manually specify everything on the command line. Usage thus would look like so:

./build.rb build redbot
./build.rb build arduino

or whatever, and all flags and arguments are neatly contained within build.rb, instead of being spread among dozens of makefiles or being manually specified on the command line

Answer 2

Make one (or more) template files that you put in a common base folder, then in each project directory place a makefile which sets flags specific to the library being built, as well as listing only the source files. Then it includes the common makefile(s) templates, which contains implicit rules and variables that takes the local flags for building.

So a structure something like this:

project root
|-- makefiles
|   |-- rules.mk
|   |-- vars.mk
|   |-- exe.mk
|   `-- lib.mk
|-- libraryA
|   |-- Makefile
|   `-- (other sources and headers for this library)
|-- libraryB
|   |-- Makefile
|   `-- (other sources and headers for this library)
|-- programA
|   |-- Makefile
|   `-- (other sources and headers for this program)
`-- programB
    |-- Makefile
    `-- (other sources and headers for this program)

The rules.mk contains rules such as clean or the implicit build rules like .c.o.

The vars.mk contains global variables and uses local flag variables to set the global flag variables like CFLAGS.

The exe.mk contains rules to make an executable program.

The lib.mk contains rules to make a library.

A local makefile will then look something like this:

LOCAL_CFLAGS = <some C flags specific to just this library/executable>

# Other local flags, e.g. LOCAL_LDFLAGS, LOCAL_LIBS, etc.

TARGET = <name of target executable/library>

LOCAL_SOURCES = <list of all source files for $(TARGET)>

LOCAL_HEADERS = <list of all headers>

include ../makefiles/vars.mk
include ../makefiles/rules.mk

include ../makefiles/exe.mk    # If making an executable
include ../makefiles/lib.mk    # If making a library
# Note: Don't include both the above two files

The vars.mk file can look something like this

CFLAGS  = <some common C flags>
CFLAGS += $(LOCAL_CFLAGS)

# All other flag variables

HEADERS = $(LOCAL_HEADERS)

CFILES   = $(filter %.c,$(LOCAL_SOURCES))
CXXFILES = $(filter %.cpp,$(LOCAL_SOURCES))

OBJECTS  = $(CFILES:%.c=%.o)
OBJECTS += $(CFILES:%.cpp=%.o)