Question

I have an FPGA design in QuartusII, and a continuous integration server with some spare capacity.

Now I'd like to build a testsuite for my FPGA design, where input signals are generated by dedicated components, and the output signals checked against expected behaviour.

Is there a way to run the simulation non-interactively from a batch file, so that warnings can be collected in a log file?

Was it helpful?

Solution

If you're using ModelSim, you can certainly run simulation from the command-line. Some instructions are available from Altera here; you can probably get more instructions directly from Mentor Graphics.

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