Your BUS
output is not a reg
, but a wire
. To use BUS
in a IF
statement (inside a combinational always
of course) BUS
has to be defined as reg
.
Something like this:
module something (input en,
output reg [15:0] bus
);
reg [15:0] data = 16'hABCD; // some value;
always @* begin
if (en)
bus = data;
else
bus = 16'hZZZZ;
end
endmodule
If bus
is going to be a wire...
module something (input en,
output [15:0] bus
);
reg [15:0] data = 16'hABCD; // some value;
assign bus = (en)? data : 16'hZZZZ;
endmodule