VHDL error Error (10822): couldn't implement registers for assignm

Question

I try to implement a JK flip flop with asynchronous Preset and Clear, with positive edge logic on clock.

I receive the following error from Altera Quartus II:

Error (10822): HDL error at JK_FF_PE_D1.vhd(52): couldn't implement registers for assignments on this clock edge

Error: Can't elaborate top-level user hierarchy

I don't see the error... I would be really grateful for a tip or a piece of advice.

Thank you in advance!

library ieee;
use ieee.std_logic_1164.all;

entity JK_FF_PE_D1 is
  port(
    J, K        : in    std_logic;  -- J, K inputs of flip flop
    PS          : in    std_logic;  -- Preset of flip flop
    CLR         : in    std_logic;  -- CLR of flip flop
    CLK         : in    std_logic;  -- Clock 
    Q, Qcompl   : out   std_logic  -- Q and its complementary output
    );
end entity JK_FF_PE_D1;

architecture simple of JK_FF_PE_D1 is
  signal temp_Q, temp_Qcompl : std_logic;

begin

  p0:process(PS, CLR, CLK) is
  begin
     case std_logic_vector'(PS, CLR) is
          when "00" =>
            temp_Q <= '1';
            temp_Qcompl <= '1';
          when "01" =>
            temp_Q <= '1';
            temp_Qcompl <= '0';
          when "10" =>
             temp_Q <= '0';
             temp_Qcompl <= '1';
          when others =>   -- Preset = 1 , Clear = 1
             if rising_edge (CLK) then  -- Clock turns from 0 -> 1
               case std_logic_vector'(J, K) is
                    when "11" =>
                      temp_Q <= not temp_Q;
                      temp_Qcompl <= not temp_Qcompl;
                    when "10" =>
                      temp_Q <= '1';
                      temp_Qcompl <= '0';
                    when "01" =>
                      temp_Q <= '0';
                      temp_Qcompl <= '1';
                    when others =>
                      null;
               end case;
             end if;
     end case;
  end process p0;
  Q <= temp_Q;
  Qcompl <= not temp_Qcompl;

end architecture simple;

Answer 1

It looks like a limitation in Altera Quartus II, since the outer case may be changed to if as shown below, and then it can run through synthesis:

p0 : process(ps, CLR, CLK) is
begin
  if std_logic_vector'(ps, CLR) = "00" then
    temp_Q      <= '1';
    temp_Qcompl <= '1';
  elsif std_logic_vector'(ps, CLR) = "01" then
    temp_Q      <= '1';
    temp_Qcompl <= '0';
  elsif std_logic_vector'(ps, CLR) = "10" then
    temp_Q      <= '0';
    temp_Qcompl <= '1';
  else                              -- Preset = 1 , Clear = 1
    if rising_edge (CLK) then       -- Clock turns from 0 -> 1
      case std_logic_vector'(J, K) is
        when "11" =>
          temp_Q      <= not temp_Q;
          temp_Qcompl <= not temp_Qcompl;
        when "10" =>
          temp_Q      <= '1';
          temp_Qcompl <= '0';
        when "01" =>
          temp_Q      <= '0';
          temp_Qcompl <= '1';
        when others =>
          null;
      end case;
    end if;
  end if;
end process p0;

If the specific target device does not allow flip flops with both asynchronous set and reset, then a warning is issued.