Can I use concatentation in a Verilog lvalue? (Possible Modelsim compiler bug?)

Question

Problem

I've been having trouble at work with the line:

{ s_b, s_a[0] } <= 2'd3;

In Modelsim 10.2c it appears to assign to b, but not to a.

Does anyone know why this does not work - and whether it is bad style in Verilog?

Full test code

`timescale 1ns/1ps
module modelsim_top_tb;
`define CLK_PERIOD 20
reg         clkin = 1'b0;
reg         aresetn = 1'b0;
always begin : clkgen
    #(`CLK_PERIOD/2) clkin <= ~clkin;
end
always @(posedge clkin) begin: rstgen
    #(`CLK_PERIOD*10) aresetn <= 1'b1;
end
initial begin
  #(`CLK_PERIOD*20)
  $stop();
end            
test1 u_test1
(
    .clk(clkin),
    .aresetn(aresetn)
);
endmodule

module test1(
  input wire clk,
  input wire aresetn);

reg [7:0] s_a;
reg s_b;

always @(posedge clk or negedge aresetn) begin
    if (!aresetn) begin
        s_a <= 8'h00;
        s_b <= 1'b0;
    end else begin
        //{s_a[0]} <= 1'd1;  // This works
        {s_b,s_a[0]} <= 2'd3; // This does not work, a is displayed as 0
        $display("a=%d b=%d",s_a,s_b);
    end
end

endmodule

Steps to reproduce

I have been testing this code with the commands:

vlib work
vmap work
vlog testcase.v
vsim -c -do "run -all; quit -f" modelsim_top_tb

In Modelsim 10.2c it prints out a value of 0 for s_a on every clock cycle.

However, if I run the same code in EDA playground, all the simulators (including Modelsim 10.1d) correctly print out a value of 1 for s_a after the first clock cycle has passed.

Answer 1

Yes, you can use concatenation in a Verilog lvalue. It looks like good coding style. It works for me on 2 other simulators (vcs and incisive); I don't have access to modelsim. I think it is a bug in Modelsim 10.2c.

Answer 2

I've reported this to Mentor as support request 2599370923 and they have fixed the bug in version 10.3 beta 2 (to be released soon).