Question

Can we start with memory address 37124H in memory address decoding for 8086/8088 microprocessors?

Here is an example of decoding address for 32k memory where the starting address is 30000H and the last address is 37FFFH:

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I think that we can't do that because the address bits of the starting address must be zeros and the address bits of the last address must be ones, and this can't be done when the starting address is 37124H.

Is that right? Is there any better answer?

Was it helpful?

Solution

You can't do it... with just a simple decoder. The requirement for an address range to be with the form of a non changing part, followed by a changing part that convers every possible combination of 0's and 1's is just to ease the circuitry: you connect the address lines of your memory to the changing bits, and the CS line of your memory to a decoder that detects whether the non changing part appears in corresponding address lines.

But you can actually build a circuit that makes possible to map some memory starting at any address you like (taking into account the granularity of the processor). Say you want to address 32KB of memory between addresses 37124h and 3F123h:

You will have to build a magnitude compare circuit, that detects whether the 20-bit address lines of the 8088/8086 processor lies between these two addresses, enabling the CS line of your memory if so.

Besides, you will need a substraction circuit that takes the 20-bit address and substracts the number 317124h from it, so at the output of this substractor, there will be an address in the range of 00000h to 07FFFh if and only if CS is enabled. The output from this substractor will go to the address lines of your memory.

The following Verilog module describes such device:

module decoder (input [19:0] busaddr, /* addr from CPU */
                output [15:0] memaddr, /* addr to memory */
                output cs_n);  /* active low CS to memory */
  assign cs_n = (busaddr >= 20'h317124 && busaddr <= 20'h3F123)? 1'b0 : 1'b1;
  assign memaddr = busaddr - 20'h317124h;
endmodule

But it needs much more hardware than a simple decoder. If the CPU is fast and memory timings are an issue, a device like this will introduce undesirable delays that may affect the performance of the system. Simple decoders, such as the one you describe, are much time efficient.

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