Parsing error in VHDL

Question

I am having this problem in coding 3bit counter with JK flip flops, and I happen to have an error in 34 line, which is written automatically, by XILINX VHDL, so I am confused in what is actually wrong.

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;

    ENTITY 3bitBrojacTest_vhd IS
    END 3bitBrojacTest_vhd;

    ARCHITECTURE behavior OF 3bitBrojacTest_vhd IS 

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Asinhroni3BitBrojacModule
PORT(
    Clk : IN std_logic;
    High : IN std_logic;       
    Q0 : INOUT std_logic;
    Q1 : INOUT std_logic;
    Q2 : INOUT std_logic;
    Q2neg : INOUT std_logic
    );
END COMPONENT;

--Inputs
SIGNAL Clk :  std_logic := '0';
SIGNAL High :  std_logic := '0';

--BiDirs
SIGNAL Q0 :  std_logic;
SIGNAL Q1 :  std_logic;
SIGNAL Q2 :  std_logic;
SIGNAL Q2neg :  std_logic;

    BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Asinhroni3BitBrojacModule PORT MAP(
    Clk => Clk,
    High => High,
    Q0 => Q0,
    Q1 => Q1,
    Q2 => Q2,
    Q2neg => Q2neg
);

clk_proc: process
begin
    Clk <= '1';
    wait for 10ns;
    Clk <= '0';
wait for 10ns;
end process;


tb : PROCESS
BEGIN

    -- Wait 100 ns for global reset to finish
    wait for 100ns;
    High <= '1';
    wait for 160ns;
    High <= '0';

    wait; -- will wait forever
END PROCESS;

    END;

So, the error says:

ERROR:HDLParsers:164 - Line 34. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER Parsing "3bitBrojacTest_vhd_stx.prj": 1.27

If anyone knows how to fix this I'd be really happy to get that answer from. Thanks guys!

Answer 1

A few potential problems:

1. I'm fairly certain your entity name is not allowed to begin with a number.

2. You need a space between your time and your suffix. (E.g. wait for 10 ns;)

3. You should not include both numeric_std and std_logic_unsigned in the same file. Just use numeric_std as this is the IEEE supported package.