Verilog Error - Quartus II - Loop Must terminate within X iterations

Question

I am working on a VERY simple verilog implementation of a RiSC16 CPU, and I am running into an issue trying compile using Quartus II Web Edition. My code is below:

reg j;
initial begin
pc = 0;
rf[0] = `ZERO;
rf[1] = `ZERO;
rf[2] = `ZERO;
rf[3] = `ZERO;
rf[4] = `ZERO;
rf[5] = `ZERO;
rf[6] = `ZERO;
rf[7] = `ZERO;
    for(j=0;j<200;j=j+1) begin // THis is line 38
        m[j] = 16'd0; 
    end
end

I am getting the following error:

Error (10106): Verilog HDL Loop error at RiSC16.v(38): loop must terminate within 10000 iterations

I am quite lost at this point. Has anyone experienced this before? Is there a syntax error somewhere?

Answer 1

Since j is declared as 1-bit, its only values are 0 and 1; it cannot reach 200, and the for loop will be infinite. Declare it as:

reg [7:0] j; // 0 to 255

or as

integer j;