Division in VHDL

Question

I am trying to divide two 32 bit std_logic_vector signals (see code below). both inputs are variable. when I write a separate module and test it, it's OK but when I use it as a part of the other module it can not be simulated. Simulation has no error but it's stopped and links me to this module. by the way I'm working with Xilinx

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity DivEx is
port(
    X   : in STD_LOGIC_VECTOR(31 downto 0);
    Y   : in STD_LOGIC_VECTOR(31 downto 0);
    R   : out STD_LOGIC_VECTOR(31 downto 0)
);
end DivEx;

architecture Behavioral of DivEx is
begin
R <= std_logic_vector(to_signed(to_integer(signed(X) / signed(Y)),32));
end Behavioral;

Answer 1

VHDL doesn't have modules. They're called component instantiations of either declared components or directly instantiated entities or configurations.

With this test bench:

library ieee;
use ieee.std_logic_1164.all;

entity tb_divex is
end entity;

architecture foo of tb_divex is
    signal x:       std_logic_vector(31 downto 0) :=x"000000FF";
    signal y:       std_logic_vector(31 downto 0) :=x"00000005";
    signal r:       std_logic_vector(31 downto 0);
begin

DUT:
    entity work.divex
        port map (
            x => x,
            y => y,
            r => r
        );

STIMULUS:
    process 
    begin
        wait for 10 ns; -- so we can see these on a waveform display
        y <= x"00000023";
        wait for 10 ns;
        x <= x"00000123";
        y <= x"00000003";
        wait for 10 ns;
        wait;      
    end process;

end architecture;

Which uses a directly instantiated entity we get:

Which shows that directly instantiating your divex results in something that works.

You never responded to Brian Drummond's request for actual warnings/error messages which also precludes someone from determining which vendor's tools you were using.

Without seeing those and your test bench or stimulus application methodology anyone answering is handicapped.

It is possible that you were using instantiation of a component via a component declaration, in which case you may not have had the component bound. You can analyze a VHDL design specification using a component declaration, but unless the entity has been previously analyzed into a design library whose contents are made visible by a context clause elaboration may not not bind the component to library design unit.

See IEEE Std 1076-1993/-2008 12.4.3/14.5.4 Component instantiation statements:

Elaboration of a component instantiation statement that instantiates a component declaration has no effect unless the component instance is either fully bound to a design entity defined by an entity declaration and architecture body or bound to a configuration of such a design entity. If a component instance is so bound, then elaboration of the corresponding component instantiation statement consists of the elaboration of the implied block statement representing the component instance and (within that block) the implied block statement representing the design entity to which the component instance is bound.

A component instantiation uses default binding based on it's name:

5.2.2/7.3.3 Default binding indication

In certain circumstances, a default binding indication will apply in the absence of an explicit binding indication. The default binding indication consists of a default entity aspect, together with a default generic map aspect and a default port map aspect, as appropriate.

If no visible entity declaration has the same simple name as that of the instantiated component, then the default entity aspect is open....

So your divex component can be open.

In some tools managing 'projects' this can occur because the design file for divex hasn't been included in the 'project'. Effectively it isn't analyzed into the current working library and when a library it has been analyzed into (a different project's working library) isn't made visible by context statement it simply isn't there.