verilog event control utilizing iff qualifier

Question

This Systemverilog tutorial lists interesting always block event control statements that utilize the iff qualifier.

I don't understand the first 3 simulation results for @1 and @2:

@0 clk 0 rst 0 enable x d x q x latch x
@1 clk 1 rst 0 enable x d 0 q 0 latch x
Reset is asserted with iff
Reset is asserted, no iff
@2 clk 0 rst 1 enable x d 0 q 0 latch x
Reset is asserted, no iff

Namely, why is reset triggering the $display statements @1 when there hasn't been a posedge rst? Also, why isn't $display(Reset is asserted with iff) triggered @2 when rst becomes 1?

Answer 1

The $display() messages are being printed at time @2. The simulator scheduler executes the $display() messages when the lines are reached. The $monitor() message is only printed at the end of the time step. Therefore, within the same time step, $display() messages will be printed before the $monitor() message. Add $time to the $display messages to help visualize this.

The final Reset is asserted, no iff is not part of time 2, but time 3. When the clock has a rising.

@3 clk 1 rst 1 enable x d 0 q 0 latch x

The "with iff" message is not displayed because iff rst == 0 masks the posedge clk from being observed when rst !=0. The posedge clk can only be observed when iff condition is true.

Do note that iff is not synthesizable, so do not put it in a design. The feature is for verification and behavioral modeling.