Here are my comments:
First, "clk" is unnecessary, as clock is implicit in Chisel.
Second, you should probably be using Bool() instead of UInt(width=1) for some of your signals.
val load = Bool(INPUT)
Although that's admittedly a stylistic opinion, but it prevents from needing to do the .toBool cast later.
Third, this line does not do what you are intending:
val bitfield = Reg(init = UInt(length))
That is creating a register that is initialized on reset to a UInt() of value "length". Instead, to create a register of width "length" do this:
val bitfield = Reg(outType=UInt(width=length))
You can also just use
val bitfield = Reg(UInt(width=length))
As the default parameter to Reg() is the "type" of register you want to create. However, IMO, that can be a bit ambiguous. If you want to initialize the register to 0, then do the following:
val bitfield = Reg(init = UInt(0, length))