Memory Access time in 2 level Paging

Question

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 ms. An average instruction takes 100 ns of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?

This was asked in GATE 2004. To solve the question, I would follow the below concept :
T(memory access avg) = .90(150) + .1(150+150+150) = 180 (150- level1, 150-level2 and 150-memory)
T effective = 100+ 2* 180 + 1/10000* 8* 10^6 = 1260.

Is this approach correct ? Also I have the following doubts :

1. There won't be a page fault when there is a TLB hit because the most frequently used pages has to be in the memory. Is it correct ?
   
2. What is the size of the page table for a process? Say for a 32 bit virtual address, for every process do we allocate a page-table with 2^32 entries ? How is the memory limits managed in paging ?

Please explain theses concepts.

Answer 1

I would suggest the following

here 100ns for instruction execution (no difference of opinion there)

Now given TLB hit ratio is 90%, so whenever there is a TLB miss, we have to do 2 memory accesses, since it is given a 2 level paging scheme.

and irrespective of TLB hit or miss 2*(150+ 8*10^6 * 1/20000 ) should be done which is memory access time for contents and overhead for page fault.

I think your expression assumes, that for an instruction whenever a TLB hit occurs for first content, it follows for the second

so you assume hit-hit or miss-miss,while since given TLB hit is 90%(per access and not per instruction), I feel there should be all 4 possible combinations

hit-hit, miss-miss, hit-miss,miss-hit