Targets are not generically generated

Question

I'm needing a somewhat generic Makefile for one of my projects, but I can't seem to get the hang of define in Makefiles.

To a minimum reduced, what I have is the following:

TARGETS = target1 target2

define TARGET_template =
$(1):
    @echo "Hi there, I'm $(1)!"
endef

.PHONY: all

all: $(TARGETS)

$(foreach TARGET, $(TARGETS), $(eval $(call TARGET_template, $(TARGET))))

And if I execute make all, I'd expect the console output to be:

Hi there, I'm target1!
Hi there, I'm target2!

But instead I get

make: *** No rule to make target `target1', needed by `all'.  Stop.

What am I doing wrong? I'm using GNU make 3.81

Answer 1

To debug uses of eval, there's a trick: you can replace the eval with info to see what make will evaluate when it gets the rule.

However, your problem is the same as this one: How to use multiple-line variable

You're reading documentation for GNU make 4.0 (or at least for a newer version than the one you're using). You need to read the docs for the version of GNU make you're actually using (3.81 was released in 2006).