Fault on CortexM0+ From LDRH Instruction

Question

I have a codebase that runs fine on the M3 architecture and am porting some code to the M0+. I am getting faults and I cannot figure out why. The exact micro I am on is the KL36Z128 (Freescale). I am using ARM-GCC-2013-Q3 release for my toolchain.

So here is the C code (it's for parsing packets as they come in so once I get enough data I just start picking out what I need to fill out the command structures):

state->cmd = *((U16*)&din[15]); // the codebase has 'legacy' type definitions

The assembly generated is:

0x4250 <+0x0014> adds r1, #15

0x4252 <+0x0016> ldrh r1, [r1, #0] <--- Faulting instruction!

0x4254 <+0x0018> strh r1, [r0, #2]

And the register values are at the time of the fault are:

r0 = 0x1ffff2cc r1 = 0x1ffffad8

I have no idea what is happening here - this seems pretty straightforward assembly. And the addressing seems OK. The Freescale datasheet says that RAM is banked with 2 sections:

SRAM_L: (0x20000000-1KB) to 0x20000000 (so it's lower section is 1/4 of the total SRAM)

SRAM_H: 0x20000000 to (0x20000000+3KB)

I originally thought that maybe something was amiss with the code being generated and what instructions can be used to access memory in the different banks - but I came up empty.

Also, the 'din' value is defined in the functions parameter list as: const U8 *din

Any thoughts?

Answer 1

state->cmd = *((U16*)&din[15]);

The * operation performs an unaligned access as din[15] element is of type uint8_t but is accessed as a uint16_t (or U16) object . Cortex-M0 / M0+ does not support unaligned access and any attempt to perform an unaligned access raises an HardFault.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/BABFAIGG.html

To fix your program, access din elements as uint8_t objects:

 state->cmd = (din[16] << 8) | din[15];