VHDL - display numbers from 0-9 with 1 sec pause

Question

I have to write program in VHDL that will display numbers from 0-9 on 'screen' with 1 sec pause (so basicly clock 0-9), and additionaly i have to check in ModelSim which makes it much harder for me. I know I shouldn't ask for such help but I only need it to my university. I'm beginner in vhdl and I have never learnt it so any clues/solution would be nice. I know i have to use sth like this:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
...
SIGNAL countSek : STD_LOGIC_VECTOR(24 DOWNTO 0);
...
BEGIN
...
-- count 1 second
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
countSec <= countSek + '1';
END IF;
END PROCESS;

PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF (Resetn = '0') THEN
licznik <= (OTHERS => '0');
ELSIF (countSek = 0) THEN
counter <= counter + '1';
END IF;
END IF;
END PROCESS;

Also I have free version of ModelSim and Ive read that i need to check my program manually. I know how to start simulation etc, but don't know what to do next (how to see in modelsim that my program actually count 0-9). Also I don't have to do check it for 50MHZ clock or something like that. Sorry for my poor english and thx in advance

Answer 1

I will try to give you some just some hints or ideas, because 1) no homeworks here and 2) i don't understand your task completely...

So my comprehension of your task is:

Make a counter which will count from 0 to 9 repetitively with a delay of 1 second.

So first, you must be clear how/where do you get your 1 second. For your purposes, there is only one way to get some time management, threw the clock of your system. So for example: Your chip/board/FPGA runs at 50MHz clock. How many clocks will you need to get one second? Well it will be clearly 50 million cycles, so you have to build a counter which will count to 50 million and then send a signal (and set itself to 0 and start counting again). With that you have your counter-module. The problem here, i doubt that ModelSim will be able (due to the free version) count to 50 million, because it usually stops simulation after some period of time. So for simulation purposes, you could set your counter to count up to, for example, 10.

So your counter process could look like (!!!no syntax check, not complete!!!):

...
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
    counter <= counter + '1';
    if( counter = SOME_NUMBER ) then
        SIGNAL_COUNTED <= '1';
        counter <= "0";
    else
        SIGNAL_COUNTER <= '0';
    end if;
END IF;
END PROCESS;

The second process of yours is your actual 0-to-9 counter. That should be really easy, if you have your delay working, you can just:

PROCESS (SIGNAL_COUNTED)
BEGIN
if(rising_edge(SIGNAL_COUNTER)) then
...

I think this should make things clear.

P.S.: I urge you to read some book about vhdl-design, to understanding for example the difference between signal and variables, how to design your entities, what is the difference between if and where statements. What is the deference between for ... generate and for ... loop etc... I know this by myself. Before VHDL i could program in C, C++, Java, Haskel, etc. but VHDL is NOT programming! If you came to VHDL from the software side, you should clarify yourself that hardware modeling is not the same and that you have to think differently.

Regards hr0m