Sensitivity List in VHDL

Question

Code from here: http://esd.cs.ucr.edu/labs/tutorial/latch.vhd

--------------------------------------------
-- Simple D Latch (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- latch is simply controlled by enable bit
-- but has nothing to do with clock signal
-- notice this difference from flip-flops
--------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;

entity D_latch is
port(   data_in:    in std_logic;
    enable:     in std_logic;
    data_out:   out std_logic
);
end D_latch;

architecture behv of D_latch is
begin       

    -- compare this to D flipflop

    process(data_in, enable)
    begin
        if (enable='1') then
            -- no clock signal here
        data_out <= data_in;  
    end if;
    end process;    

end behv;

Why does the "data_in" need to be in the sensitivity list? I know the process needs it for assignment however the process functions based on the enable input.

Thanks

Answer 1

For a D-latch you want that data_out=data_in as long as enable is '1'. So if data_in changes while enable remains '1', data_out has to change. If data_in where not in the sensitivity list, this would not happen.