Rising edge detection sysverilog

Question

module syncrisedgedetect(input logic sig_a, rst,clk,output logic sig_a_risedge);

  logic sig_a_d1;

  always @(posedge clk or negedge rst)
  begin
    if(!rst)
      sig_a_d1<=1'b0;
    else
      sig_a_d1<=sig_a;
  end

  assign sig_a_risedge=sig_a & !sig_a_d1;

endmodule

Hi, I came across this code in a book regarding rising edge detection for sig_a. Can anybody explain me its working?

Thanks

Answer 1

This is a basic synchronous edge detection circuit.

The input, sig_a, is sampled on each rising edge of the clock, clk. The sampled value is registered; that is, sig_a_d1 is the value of sig_a delayed by one clock cycle.

The output will go to a 1 when there is a rising edge on the input. The assignment to sig_a_risedge is responsible for this. It says that "there was a rising edge on sig_a if the current value is 1 and the value on the previous clock cycle was 0".

Note that this will only work properly if the frequency of the input signal is lower than that of clock. If the input goes 0 -> 1 -> 0 all within a single clock period of the sampling clock, the edge may be missed.