malformed statement in verilog

Question

Hi i am using the folowing code to design a n-bit counter. Depending on the start and end i want to instantiate up or down counter.

But i am getting "Malformed statement". Please help.

module nbitUpCounter(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;

    output reg [n:0] count;
    input  [n:0] startc;
    input  [n:0] endc;
    input clk;
    input rst_n;
    input actlow;

    // Increment count on clock
    always @(actlow or posedge clk or negedge rst_n)
    begin
       if (actlow == 0)
       begin
           if (rst_n==0) 
          count = startc;
       else if (count==endc) count=startc;
           else count = count + 1;
       end
    end
endmodule

module nbitDownCounter(startc,endc , clk, rst_n,actlow,count);

parameter n = 7;

    output reg [n:0] count;
    input  [n:0] startc;
    input  [n:0] endc;
    input clk;
    input rst_n;
    input actlow;

    // Increment count on clock
    always @(actlow or posedge clk or negedge rst_n)
    begin
       if (actlow == 0)
       begin
           if (rst_n==0) 
          count = startc;
       else if (count==endc) count=startc;
           else count = count - 1;
       end
    end
endmodule

module Init(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;

    output wire [n:0] count;
    input  [n:0] startc;
    input  [n:0] endc;
    input clk;
    input rst_n;
    input actlow;
generate
    initial
    begin
        if(startc>endc)
        nbitDownCounter c(startc, endc, C_t,rst_t,actlow,count);
    end
endgenerate
endmodule

module Testbench;

    reg [7:0] startc, endc;
    reg C_t, rst_t;
    reg actlow;
    wire [7:0] outc;

    initial
    begin

    //case 0
    startc <= 8'b00000011; endc <= 8'b0000001;
    //Init i(startc,endc,C_t,rst_t,actlow,count);
    actlow<=0;
    C_t <=1; rst_t <=0;
    #1 $display("count = %b",outc );
    //case1

    rst_t<=1;C_t<=0;C_t<=1;
    #1 $display("count = %b",outc );

    //Case3
    C_t<=0;C_t<=1;
    #1 $display("count = %b",outc );
    //Case3
    C_t<=0;C_t<=1;
    #1 $display("count = %b",outc );
    end
endmodule

Answer 1

You're trying to instantiate your module in an initial block, which is illegal. Removing the initial begin inside module Init should solve the problem. Have a look at this page for an example: http://asic-soc.blogspot.de/2012/06/verilog-hdl-generate-blocks.html