The sen=0010
appears like sen
is compared to a 4-bit vector, but it is
actually compare with the decimal value 0010 = 10 = ten, due to the lack of
""
around the 0010
value. Fix this in all place with by adding ""
, like
"0010"
.
VHDL is basically strong typed, but the use ieee.std_logic_unsigned.all;
adds
functions that allows compare between std_logic_vector
and integer
, and for
this reason the problem passes syntax check.
Also:
- Fix a syntax error by adding
begin
before theprocess
, since that is required inarchitecture
- Consider using if
rising_edge(clk)
instead ofwait until clk'event and clk='1'
- Consider rewrite with
case